AMD visar upp Bulldozerprocessorn Orochi

A good way to express what Bulldozer is can be summed up as “slimmed down, but double wide”. For each traditional core, AMD has instituted a dual ALU design with robust floating point and SSE units. Each core can handle two threads, like SMT, but actually has separate execution units which each process individual threads without sharing execution resources.

Each unit features a single fetch and decode stage. The decode stage is comprised of four units, but we do not yet know their inner workings. In the previous K7/K10.5 generations of parts, there are three complex decode units. On the Intel side with Core 2 and Nehalem, there are three simple decode units and a single complex. AMD also did not cover subjects such as macro-ops and macro-op fusion. AMD has beefed up their decode stage significantly though. It simply had to, because it is now feeding dual integer schedulers and a floating point scheduler feeding 2 x 128 bit FMACs and MMX units.